The Single-Port Gigabit Ethernet Server Adapter I210 (Single Pack) from Intel is a low-halogen PCIe 10/100/1000 Ethernet adapter, designed for entry-level servers and audio-video applications. It offers innovative power management features, including Energy Efficient Ethernet (EEE), DMA Coalescing, ultra-compact design, and a ventilated bracket for increased efficiency and reduced power consumption. It supports PCIe Gen 2.1 (2.5 GT/s) and IEEE 802.1Qav Audio-Video Bridging (AVB) for tightly controlled media stream synchronization, buffering, and reservation.
The I210 Ethernet Controller supports IEEE 802.1Qav Audio-Video Bridging (AVB) for customers requiring tightly controlled media stream synchronization, buffering, and reservation. 802.1Qav is part of the AVB specification, which provides a way to bounded latency and latency variation for time sensitive traffic. AVB includes timing and synchronization for time specific applications, (802.1AS) Stream Reservation (SR) protocol, to guarantee the resources needed for Audio/Video (AV) streams (802.1Qat). It also includes forwarding and queuing enhancements for time sensitive streams (802.1Qav). The adapter is low halogen and completely lead-free to reduce the environmental impact. It maximizes airflow and cooling with a ventilated bracket. This server adapter contains four transmit and four receive queues. These queues offer ECC memory for improved data reliability. The adapter efficiently manages packets with minimum latency by combining parallel and pipelined logic architectures, optimized for these independent transmit and receive queues. These queues, combined with Receive Side Scaling (RSS) and Message Signal Interrupt Extension (MSI-X) support, optimize the performance on servers with multi-core processors. Energy Efficient Ethernet (EEE) reduces the power consumption of an Ethernet connection during periods of low network activity by negotiating with a compliant EEE switch port to transition to a Low Power Idle (LPI) state. EEE is supported for both 1000BASE-T and 100BASE-TX. DMA request is initiated to place the packet into host (or server) memory, when a packet arrives at the adapter. This transaction wakes up the processor, memory, and other system components from a lower power state in order to perform the tasks required to handle the incoming packet. Based on the configurable DMAC settings, incoming packets are buffered momentarily before any DMA calls are made. This enables the controller to intelligently identify opportunities to batch multiple packets together, so that when components are wakened from lower power states, they can efficiently handle the batched packets at the same time. It also enables the platform components to remain in lower power states longer, which can reduce platform energy consumption. DMAC synchronizes DMA calls across all controller ports to ensure maximum power savings.Ethernet Features
Audio-Video Bridging (AVB) Support (802.1Qav)
Dedicated Tx and Rx queues for AVB traffic
Supports forwarding and queuing enhancements for time-sensitive streams
Supports time-based transmission
IEEE 802.3 Auto-Negotiation
Automatic link configuration for speed duplex and flow control
Compliant with 1 Gb/s Ethernet IEEE 802.3, 802.3u, 802.3ab PHY Specifications
Robust operation over installed base of Cat 5 twisted-pair cabling
Integrated PHY for 10/100/1000 Mb/s for Multi-Speed, Full, and Half-Duplex
Smaller footprint and lower power dissipation compared to multiple discrete MAC and PHYs
IEEE 802.3x and IEEE 802.3z Compliant
IEEE 802.3x and IEEE 802.3z compliant flow control support, with software-controllable Rx thresholds and Tx pause frames
Local control of network congestion levels
Frame loss reduced from receive overruns
Automatic Cross-Over Detection Function (MDI/MDI-X)
The PHY automatically detects which application is being used and configures itself accordingly
IEEE 1588 Protocol and 802.1AS Implementation
Time-stamping and synchronization of time sensitive applications
Distribute common time to media devices
Power Management
IEEE 802.3az
Power consumption by the PHY is reduced by 50% approximately
Link transitions to Low Power Idle (LPI) state as defined in the IEEE 802.3az standard
DMA Coalescing
Reduces platform power consumption by coalescing, aligning, and synchronizing DMA
Enables synchronizing port activity and power management of memory, CPU and RC internal circuitry
Smart Power Down (SPD) at S0 No Link/Sx No Link
PHY powers down circuits and clocks that are not required for detection of link activity
Active State Power Management (ASPM)
Optionality Compliance bit enables ASPM or runs ASPM compliance tests to support entry to L0s
LAN Disable Function
Option to disable the LAN port and/or PCIe function. Disabling just the PCIe function but keeping the LAN port that resides on it fully active (for manageability purposes and BMC pass-through traffic)
Full Wake up Support
Advanced Power Management (APM) Support
Designed to receive a broadcast or unicast packet with an explicit data pattern (Magic Packet), and assert a signal to wake up the system
Advanced Configuration and Power Interface (ACPI) Specification v2.0c
PCIe power management based wake-up, that can generate system wake-up events from a number of sources
Magic packet wake-up enabled with unique MAC address
ACPI Register Set and Power Down Functionality Supporting D0/D3 States
A power-managed link speed control lowers link speed (and power) when high link performance is not required
MAC Power Management Controls
Power management controls in the MAC/PHY enable the device to enter a low-power state
Low Power Link Up - Link Speed Control
Enables a link to come up at low-speed in cases, where the power is more important than the performance
Power Management Protocol Offload (Proxying)
Avoid spurious wake-up events and reduce system power consumption, when the device is in D3 low power state, and system is in S3 or S4 low power states
Stateless Offloads and Performance Features
TCP/UDP, IPv4 Checksum Offloads (Rx/Tx/Large-Send), Extended Tx Descriptors
Checksum and segmentation capability extended to new standard packet type
IPv6 Support for IP/TCP and IP/UDP Receive Checksum Offload
It improves CPU usage
Transmit Segmentation Offloading (TSO) (IPv4, IPv6)
Increased throughput and lower processor usage
Interrupt Throttling Control
Limits maximum interrupt rate and improves CPU usage
Legacy and Message Signal Interrupt (MSI)
Interrupt mapping
Message Signal Interrupt Extension (MSI-X)
Dynamic allocation of up to 5 vectors per port
Intelligent Interrupt Generation
Enhanced software device driver performance
Receive Side Scaling (RSS) for Windows
Up to four queues per port
Scalable I/O for Linux Environments (IPv4, IPv6, TCP/UDP)
Improves the system performance related to handling of network data on multiprocessor systems
Jumbo Frames
Support for packets up to 9.5KB and enables faster, and more accurate throughput of data
Low Latency Interrupts
Based on the sensitivity of incoming data, the controller can bypass the automatic moderation of time intervals between the interrupts
Header/Packet Data Split in Receive
Helps the driver to focus on the relevant part of the packet without the need to parse it
PCIe v2.1 TLP Processing Hint Requester
Provides hints on a per transaction basis to facilitate optimized processing
Remote Boot Option Features
Preboot eXecution Environment (PXE) Flash Interface Support
Enables system boot up via the EFI (32 and 64-bit)
Flash interface for PXE 2.1 option ROM
Intel iSCSI Remote Boot for Windows, Linux, and VMware
Enables system boot up via iSCSI
Provides additional network management capability
Intel Boot Agent Software
Enables networked computer to boot using a program code image supplied by a remote server, complies with the Preboot eXecution Environment (PXE) version 2.1 specification
Note:
Linux boot via PXE or BOOTP, Windows Deployment Services, or UEFI
Descriptor Ring Management Hardware for Transmit and Receive
Optimized descriptor fetch and write-back for efficient system memory, and PCIe bandwidth usage
Manageability Features
DMTF Network Controller Sideband Interface (NC-SI) Pass-Through
Supports pass-through traffic between BMC and controller's LAN functions
Meets RMII specification, revision 1.2 as a PHY-side dev
Intel System Management Bus (SMBus) Pass-Through
Enables BMC to configure the controller's filters and management related capabilities
Management Component Transport Protocol (MCTP) Over SMBus and PCIe
Used for baseboard management controller (BMC) communication between add-in devices
OS2BMC Traffic Support
Transmission and reception of traffic internally to communicate between the OS and local BMC
Private OS2BMC Traffic Flow
BMC may have its own private connection to the network controller and network flows are blocked
Firmware Based Thermal Management
Can be programmed via the BMC to initiate thermal actions and report thermal occurrences
IEEE 802.3 MII Management Interface
Enables the MAC and software to monitor and control the state of the PHY
MAC/PHY Control and Status
Enhanced control capabilities through PHY reset, link status, duplex indication, and MAC Dx power state
Watchdog Timer
Defined by the FLASHT register to minimize flash updates
Extended Error Reporting
Messaging support to communicate multiple types/severity of errors
Controller Memory Protection
Main internal memories are protected by Error Correcting Code (ECC) or parity bits
Vital Product Data (VPD) Support
Support for VPD memory area
UPC: 735858257817